lab2

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    00:42:53 10/29/2015
// Design Name:
// Module Name:    rotary_controller
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rotary_controller #(parameter DATA_ADDR = 32'h00000500, parameter STEP_ADDR = 32'h00000501) (
    //controller
     output [7:0] LED,
    input ROT_A,
    input ROT_B,
     //wishbone
    inout clk_i,
    inout rst_i,
    input [31:0] ADDR_I,
    input WE_I,
    input [31:0] DATA_I,
    output reg [31:0] DATA_O,
    input CYC_I,
    input STB_I,
    output ACK_O
    );

localparam IDLE = 0;
localparam ACK  = 1;

reg state_r;

reg[7:0] data;
reg[7:0] step;

wire read  = cyc_i & stb_i & !we_i;
wire write = cyc_i & stb_i & we_i;

always@(posedge clk_i, posedge rst_i)
    if(rst_i) begin
        ACK_O   <= 0;
        DATA_O   <= 0;
          data <= 8'b0;
          step <= 8'b0;
    end else begin

          ACK_O   <= 0;

          case(state_r)
            IDLE:
                begin
                    if(write) begin
                                case(ADDR_I)
                                    DATA_ADDR:
                                        begin
                                            data <= DATA_I[7:0];
                                            state_r <= 1;
                                            ACK_O   <= 1'b1;
                                        end
                                    STEP_ADDR:
                                        begin
                                            step <= DATA_I[7:0];
                                            state_r <= 1;
                                            ACK_O   <= 1'b1;
                                        end
                                    default:
                                        begin
                                        end
                                endcase
                    end else if(read) begin
                                DATA_O <= 32'b0;
                                case(ADDR_I)
                                    DATA_ADDR:
                                        begin
                                            DATA_O[7:0] <= data;
                                            state_r <= 1;
                                        end
                                    STEP_ADDR:
                                        begin
                                            DATA_O[7:0] <= step;
                                            state_r <= 1;
                                        end
                                    default:
                                        begin
                                        end
                                endcase
                    end
                end
            ACK:
                begin
                    ack_o   <= 1'b0;
                    state_r <= IDLE;
                end
        endcase
     end
endmodule