module main(
    input clk,
    input com[31:0],
    input t[31:0],
    input op1[31:0],
    input op2[31:0],
    input rst,
    output addr)

         //opcodes
     localparam         BEQ   = 6'b000100,
                    J     = 6'd2;
     //--------------------------------

    wire next_addr[31:0];
    wire cur_addr[31:0];
    wire opcode[5:0] <= com[31:26];
    wire sign_ext[31:0] <= com[15:0] ;
    wire jmp_adr[24:0] = com[24:0];

    assign sign_ext = sign_ext << 16; //или на 2?

    ps ps_my(
        .clk(clk),
        .rst(rst),
        .next_val(next_addr),
        .addr(cur_addr)
    );

    always@(posedge clk) begin
        if(opcode == BEQ) begin
            if(op1 == op2)
                next_addr = sign_ext + t;
            else
                next_addr = cur_addr + 4;
        end
        else if (opcode == J) begin
                next_addr = (cur_addr & 8'hf0000000) | (jmp_adr << 2); //или на 16?
        end
        else begin
                next_addr = cur_addr + 4;
        end

    end

endmodule

module ps(
    input clk,
    input rst,
    input next_val[31:0],
    output addr[31:0])

    always@(posedge clk,posedge rst) begin
        if(rst)
            addr<=0;
        else
            addr<=next_val;
    end
endmodule