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  1. # cat /usr/src/uClinux-dist-2010R1-RC5/linux-2.6.x/arch/blackfin/mach-bf533/boards/ip0x.c
  2.  
  3. /*
  4. * Copyright 2004-2009 Analog Devices Inc.
  5. * 2007 David Rowe
  6. * 2006 Intratrade Ltd.
  7. * Ivan Danov <idanov@gmail.com>
  8. * 2005 National ICT Australia (NICTA)
  9. * Aidan Williams <aidan@nicta.com.au>
  10. *
  11. * Licensed under the GPL-2 or later.
  12. */
  13.  
  14. #include <linux/device.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mtd/mtd.h>
  17. #include <linux/mtd/nand.h>
  18. #include <linux/mtd/partitions.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/spi/flash.h>
  21. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  22. #include <linux/usb/isp1362.h>
  23. #endif
  24. #include <asm/irq.h>
  25. #include <asm/dma.h>
  26. #include <asm/bfin5xx_spi.h>
  27. #include <asm/portmux.h>
  28.  
  29. //#include <linux/slab.h>
  30. //#include <linux/init.h>
  31. //#include <linux/module.h>
  32.  
  33. //#include <asm/blackfin.h>
  34. //#include <asm/gpio.h>
  35. #include <asm-generic/io.h>
  36.  
  37. /*
  38. * Name the Board for the /proc/cpuinfo
  39. */
  40. const char bfin_board_name[] = "IP04/IP08";
  41.  
  42. /*
  43. * Driver needs to know address, irq and flag pin.
  44. */
  45. #if defined(CONFIG_BFIN532_IP0X)
  46. #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
  47.  
  48. #include <linux/dm9000.h>
  49.  
  50. static struct resource dm9000_resource1[] = {
  51. {
  52. .start = 0x20100000,
  53. .end = 0x20100000 + 1,
  54. .flags = IORESOURCE_MEM
  55. },{
  56. .start = 0x20100000 + 2,
  57. .end = 0x20100000 + 3,
  58. .flags = IORESOURCE_MEM
  59. },{
  60. .start = IRQ_PF15,
  61. .end = IRQ_PF15,
  62. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
  63. }
  64. };
  65.  
  66. static struct resource dm9000_resource2[] = {
  67. {
  68. .start = 0x20200000,
  69. .end = 0x20200000 + 1,
  70. .flags = IORESOURCE_MEM
  71. },{
  72. .start = 0x20200000 + 2,
  73. .end = 0x20200000 + 3,
  74. .flags = IORESOURCE_MEM
  75. },{
  76. .start = IRQ_PF14,
  77. .end = IRQ_PF14,
  78. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
  79. }
  80. };
  81.  
  82. /*
  83. * for the moment we limit ourselves to 16bit IO until some
  84. * better IO routines can be written and tested
  85. */
  86. static struct dm9000_plat_data dm9000_platdata1 = {
  87. .flags = DM9000_PLATF_16BITONLY,
  88. };
  89.  
  90. static struct platform_device dm9000_device1 = {
  91. .name = "dm9000",
  92. .id = 0,
  93. .num_resources = ARRAY_SIZE(dm9000_resource1),
  94. .resource = dm9000_resource1,
  95. .dev = {
  96. .platform_data = &dm9000_platdata1,
  97. }
  98. };
  99.  
  100. static struct dm9000_plat_data dm9000_platdata2 = {
  101. .flags = DM9000_PLATF_16BITONLY,
  102. };
  103.  
  104. static struct platform_device dm9000_device2 = {
  105. .name = "dm9000",
  106. .id = 1,
  107. .num_resources = ARRAY_SIZE(dm9000_resource2),
  108. .resource = dm9000_resource2,
  109. .dev = {
  110. .platform_data = &dm9000_platdata2,
  111. }
  112. };
  113.  
  114. #endif
  115. #endif
  116.  
  117.  
  118. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  119. /* all SPI peripherals info goes here */
  120.  
  121. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  122. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  123. .enable_dma = 0, /* if 1 - block!!! */
  124. .bits_per_word = 8,
  125. };
  126. #endif
  127.  
  128. /* Notice: for blackfin, the speed_hz is the value of register
  129. * SPI_BAUD, not the real baudrate */
  130. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  131. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  132. {
  133. .modalias = "mmc_spi",
  134. .max_speed_hz = 2,
  135. .bus_num = 1,
  136. .chip_select = 5,
  137. .controller_data = &mmc_spi_chip_info,
  138. },
  139. #endif
  140. };
  141.  
  142. /* SPI controller data */
  143. static struct bfin5xx_spi_master spi_bfin_master_info = {
  144. .num_chipselect = 8,
  145. .enable_dma = 1, /* master has the ability to do dma transfer */
  146. };
  147.  
  148. static struct platform_device spi_bfin_master_device = {
  149. .name = "bfin-spi-master",
  150. .id = 1, /* Bus number */
  151. .dev = {
  152. .platform_data = &spi_bfin_master_info, /* Passed to driver */
  153. },
  154. };
  155. #endif /* spi master and devices */
  156.  
  157. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  158. #ifdef CONFIG_SERIAL_BFIN_UART0
  159. static struct resource bfin_uart0_resources[] = {
  160. {
  161. .start = BFIN_UART_THR,
  162. .end = BFIN_UART_GCTL+2,
  163. .flags = IORESOURCE_MEM,
  164. },
  165. {
  166. .start = IRQ_UART0_RX,
  167. .end = IRQ_UART0_RX + 1,
  168. .flags = IORESOURCE_IRQ,
  169. },
  170. {
  171. .start = IRQ_UART0_ERROR,
  172. .end = IRQ_UART0_ERROR,
  173. .flags = IORESOURCE_IRQ,
  174. },
  175. {
  176. .start = CH_UART0_TX,
  177. .end = CH_UART0_TX,
  178. .flags = IORESOURCE_DMA,
  179. },
  180. {
  181. .start = CH_UART0_RX,
  182. .end = CH_UART0_RX,
  183. .flags = IORESOURCE_DMA,
  184. },
  185. };
  186.  
  187. unsigned short bfin_uart0_peripherals[] = {
  188. P_UART0_TX, P_UART0_RX, 0
  189. };
  190.  
  191. static struct platform_device bfin_uart0_device = {
  192. .name = "bfin-uart",
  193. .id = 0,
  194. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  195. .resource = bfin_uart0_resources,
  196. .dev = {
  197. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  198. },
  199. };
  200. #endif
  201. #endif
  202.  
  203. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  204. #ifdef CONFIG_BFIN_SIR0
  205. static struct resource bfin_sir0_resources[] = {
  206. {
  207. .start = 0xFFC00400,
  208. .end = 0xFFC004FF,
  209. .flags = IORESOURCE_MEM,
  210. },
  211. {
  212. .start = IRQ_UART0_RX,
  213. .end = IRQ_UART0_RX+1,
  214. .flags = IORESOURCE_IRQ,
  215. },
  216. {
  217. .start = CH_UART0_RX,
  218. .end = CH_UART0_RX+1,
  219. .flags = IORESOURCE_DMA,
  220. },
  221. };
  222.  
  223. static struct platform_device bfin_sir0_device = {
  224. .name = "bfin_sir",
  225. .id = 0,
  226. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  227. .resource = bfin_sir0_resources,
  228. };
  229. #endif
  230. #endif
  231.  
  232. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  233. static struct resource isp1362_hcd_resources[] = {
  234. {
  235. .start = 0x20300000,
  236. .end = 0x20300000 + 1,
  237. .flags = IORESOURCE_MEM,
  238. },{
  239. .start = 0x20300000 + 2,
  240. .end = 0x20300000 + 3,
  241. .flags = IORESOURCE_MEM,
  242. },{
  243. .start = IRQ_PF11,
  244. .end = IRQ_PF11,
  245. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
  246. },
  247. };
  248.  
  249. static struct isp1362_platform_data isp1362_priv = {
  250. .sel15Kres = 1,
  251. .clknotstop = 0,
  252. .oc_enable = 0, /* external OC */
  253. .int_act_high = 0,
  254. .int_edge_triggered = 0,
  255. .remote_wakeup_connected = 0,
  256. .no_power_switching = 1,
  257. .power_switching_mode = 0,
  258. };
  259.  
  260. static struct platform_device isp1362_hcd_device = {
  261. .name = "isp1362-hcd",
  262. .id = 0,
  263. .dev = {
  264. .platform_data = &isp1362_priv,
  265. },
  266. .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
  267. .resource = isp1362_hcd_resources,
  268. };
  269. #endif
  270.  
  271. #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
  272.  
  273.  
  274. #ifdef CONFIG_MTD_PARTITIONS
  275. const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
  276.  
  277. static struct mtd_partition bfin_plat_nand_partitions[] = {
  278. {
  279. .name = "linux kernel(nand)",
  280. .size = 0x800000,
  281. .offset = 0,
  282. }, {
  283. .name = "file system(nand)",
  284. //.size = MTDPART_SIZ_FULL,
  285. //Note: in linux-2.6.x/.config: CONFIG_BFIN_NAND_PLAT_SIZE=0x10000000
  286. .size = (CONFIG_BFIN_NAND_PLAT_SIZE-0x800000),
  287. //.offset = MTDPART_OFS_APPEND,
  288. .offset = 0x800000,
  289. },
  290. };
  291. #endif
  292.  
  293. //#define BFIN_NAND_BASE CONFIG_BFIN_NAND_BASE */
  294. #define BFIN_NAND_BASE CONFIG_BFIN_NAND_PLAT_BASE
  295.  
  296. //#define BFIN_NAND_CLE (1<<CONFIG_BFIN_NAND_CLE) */ /* Ax -> Command Enable */
  297. //#define BFIN_NAND_ALE (1<<CONFIG_BFIN_NAND_ALE) /* Ax -> Address Enable */
  298. #define BFIN_NAND_PLAT_CLE (1<<CONFIG_BFIN_NAND_PLAT_CLE) /* Ax -> Command Enable */
  299. #define BFIN_NAND_PLAT_ALE (1<<CONFIG_BFIN_NAND_PLAT_ALE) /* Ax -> Address Enable */
  300.  
  301. //#define BFIN_NAND_PLAT_CLE 2
  302. //#define BFIN_NAND_PLAT_ALE 1
  303.  
  304. static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  305. {
  306. struct nand_chip *this = mtd->priv;
  307.  
  308. if (cmd == NAND_CMD_NONE)
  309. return;
  310.  
  311. if (ctrl & NAND_CLE)
  312. writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
  313. else
  314. writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
  315. }
  316.  
  317. #define BFIN_NAND_PLAT_READY GPIO_PF3
  318. static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
  319. {
  320. return gpio_get_value(BFIN_NAND_PLAT_READY);
  321. }
  322.  
  323. static struct platform_nand_data bfin_plat_nand_data = {
  324. .chip = {
  325. .nr_chips = 1,
  326. .chip_delay = 30,
  327. #ifdef CONFIG_MTD_PARTITIONS
  328. .part_probe_types = part_probes,
  329. .partitions = bfin_plat_nand_partitions,
  330. .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
  331. #endif
  332. },
  333. .ctrl = {
  334. .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
  335. .dev_ready = bfin_plat_nand_dev_ready,
  336. },
  337. };
  338.  
  339. #define MAX(x, y) (x > y ? x : y)
  340. static struct resource bfin_plat_nand_resources = {
  341. //.start = 0x20212000,
  342. .start = 0x20000000,
  343. //.end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
  344. .end = 0x20000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
  345. .flags = IORESOURCE_MEM,
  346. };
  347.  
  348. static struct platform_device bfin_async_nand_device = {
  349. .name = "gen_nand",
  350. .id = -1,
  351. .num_resources = 1,
  352. .resource = &bfin_plat_nand_resources,
  353. .dev = {
  354. .platform_data = &bfin_plat_nand_data,
  355. },
  356. };
  357.  
  358. static void bfin_plat_nand_init(void)
  359. {
  360. gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
  361.  
  362. //Added by me
  363. printk("CLE is %d and ALE is %d\n",BFIN_NAND_PLAT_CLE,BFIN_NAND_PLAT_ALE);
  364. }
  365. #else
  366. static void bfin_plat_nand_init(void) {}
  367. #endif
  368.  
  369. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  370. static struct mtd_partition stamp_partitions[] = {
  371. {
  372. .name = "bootloader(nor)",
  373. .size = 0x40000,
  374. .offset = 0,
  375. }, {
  376. .name = "linux kernel(nor)",
  377. .size = 0x180000,
  378. .offset = MTDPART_OFS_APPEND,
  379. }, {
  380. .name = "file system(nor)",
  381. .size = 0x400000 - 0x40000 - 0x180000 - 0x10000,
  382. .offset = MTDPART_OFS_APPEND,
  383. }, {
  384. .name = "MAC Address(nor)",
  385. .size = MTDPART_SIZ_FULL,
  386. .offset = 0x3F0000,
  387. .mask_flags = MTD_WRITEABLE,
  388. }
  389. };
  390.  
  391. static struct physmap_flash_data stamp_flash_data = {
  392. .width = 2,
  393. .parts = stamp_partitions,
  394. .nr_parts = ARRAY_SIZE(stamp_partitions),
  395. #ifdef CONFIG_ROMKERNEL
  396. .probe_type = "map_rom",
  397. #endif
  398. };
  399.  
  400. static struct resource stamp_flash_resource = {
  401. .start = 0x20000000,
  402. .end = 0x203fffff,
  403. .flags = IORESOURCE_MEM,
  404. };
  405.  
  406. static struct platform_device stamp_flash_device = {
  407. .name = "physmap-flash",
  408. .id = 0,
  409. .dev = {
  410. .platform_data = &stamp_flash_data,
  411. },
  412. .num_resources = 1,
  413. .resource = &stamp_flash_resource,
  414. };
  415. #endif
  416.  
  417. static struct platform_device *ip0x_devices[] __initdata = {
  418. #if defined(CONFIG_BFIN532_IP0X)
  419. #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
  420. &dm9000_device1,
  421. &dm9000_device2,
  422. #endif
  423. #endif
  424.  
  425. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  426. &spi_bfin_master_device,
  427. #endif
  428.  
  429. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  430. #ifdef CONFIG_SERIAL_BFIN_UART0
  431. &bfin_uart0_device,
  432. #endif
  433. #endif
  434.  
  435. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  436. #ifdef CONFIG_BFIN_SIR0
  437. &bfin_sir0_device,
  438. #endif
  439. #endif
  440.  
  441. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  442. &isp1362_hcd_device,
  443. #endif
  444.  
  445. #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
  446. &bfin_async_nand_device,
  447. #endif
  448. };
  449.  
  450. static int __init ip0x_init(void)
  451. {
  452. int i;
  453.  
  454. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  455. bfin_plat_nand_init();
  456. platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
  457.  
  458. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  459. for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) {
  460. int j = 1 << bfin_spi_board_info[i].chip_select;
  461. /* set spi cs to 1 */
  462. bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j);
  463. bfin_write_FIO_FLAG_S(j);
  464. }
  465. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  466. #endif
  467.  
  468. return 0;
  469. }
  470.  
  471. arch_initcall(ip0x_init);
  472.  
  473. static struct platform_device *ip0x_early_devices[] __initdata = {
  474. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  475. #ifdef CONFIG_SERIAL_BFIN_UART0
  476. &bfin_uart0_device,
  477. #endif
  478. #endif
  479. };
  480.  
  481. void __init native_machine_early_platform_add_devices(void)
  482. {
  483. printk(KERN_INFO "register early platform devices\n");
  484. early_platform_add_devices(ip0x_early_devices,
  485. ARRAY_SIZE(ip0x_early_devices));
  486. }
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