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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2007 David Rowe
  4. * 2006 Intratrade Ltd.
  5. * Ivan Danov <idanov@gmail.com>
  6. * 2005 National ICT Australia (NICTA)
  7. * Aidan Williams <aidan@nicta.com.au>
  8. *
  9. * Licensed under the GPL-2 or later.
  10. */
  11.  
  12. #include <linux/device.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/mtd/mtd.h>
  15. #include <linux/mtd/nand.h>
  16. #include <linux/mtd/partitions.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/spi/flash.h>
  19. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  20. #include <linux/usb/isp1362.h>
  21. #endif
  22. #include <asm/irq.h>
  23. #include <asm/dma.h>
  24. #include <asm/bfin5xx_spi.h>
  25. #include <asm/portmux.h>
  26.  
  27. #include <asm-generic/io.h>
  28.  
  29. /*
  30. * Name the Board for the /proc/cpuinfo
  31. */
  32. const char bfin_board_name[] = "IP04/IP08";
  33.  
  34. /*
  35. * Driver needs to know address, irq and flag pin.
  36. */
  37. #if defined(CONFIG_BFIN532_IP0X)
  38. #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
  39.  
  40. #include <linux/dm9000.h>
  41.  
  42. static struct resource dm9000_resource1[] = {
  43. {
  44. .start = 0x20100000,
  45. .end = 0x20100000 + 1,
  46. .flags = IORESOURCE_MEM
  47. },{
  48. .start = 0x20100000 + 2,
  49. .end = 0x20100000 + 3,
  50. .flags = IORESOURCE_MEM
  51. },{
  52. .start = IRQ_PF15,
  53. .end = IRQ_PF15,
  54. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
  55. }
  56. };
  57.  
  58. static struct resource dm9000_resource2[] = {
  59. {
  60. .start = 0x20200000,
  61. .end = 0x20200000 + 1,
  62. .flags = IORESOURCE_MEM
  63. },{
  64. .start = 0x20200000 + 2,
  65. .end = 0x20200000 + 3,
  66. .flags = IORESOURCE_MEM
  67. },{
  68. .start = IRQ_PF14,
  69. .end = IRQ_PF14,
  70. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
  71. }
  72. };
  73.  
  74. /*
  75. * for the moment we limit ourselves to 16bit IO until some
  76. * better IO routines can be written and tested
  77. */
  78. static struct dm9000_plat_data dm9000_platdata1 = {
  79. .flags = DM9000_PLATF_16BITONLY,
  80. };
  81.  
  82. static struct platform_device dm9000_device1 = {
  83. .name = "dm9000",
  84. .id = 0,
  85. .num_resources = ARRAY_SIZE(dm9000_resource1),
  86. .resource = dm9000_resource1,
  87. .dev = {
  88. .platform_data = &dm9000_platdata1,
  89. }
  90. };
  91.  
  92. static struct dm9000_plat_data dm9000_platdata2 = {
  93. .flags = DM9000_PLATF_16BITONLY,
  94. };
  95.  
  96. static struct platform_device dm9000_device2 = {
  97. .name = "dm9000",
  98. .id = 1,
  99. .num_resources = ARRAY_SIZE(dm9000_resource2),
  100. .resource = dm9000_resource2,
  101. .dev = {
  102. .platform_data = &dm9000_platdata2,
  103. }
  104. };
  105.  
  106. #endif
  107. #endif
  108.  
  109.  
  110. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  111. /* all SPI peripherals info goes here */
  112.  
  113. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  114. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  115. .enable_dma = 0, /* if 1 - block!!! */
  116. .bits_per_word = 8,
  117. };
  118. #endif
  119.  
  120. /* Notice: for blackfin, the speed_hz is the value of register
  121. * SPI_BAUD, not the real baudrate */
  122. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  123. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  124. {
  125. .modalias = "mmc_spi",
  126. .max_speed_hz = 2,
  127. .bus_num = 1,
  128. .chip_select = 5,
  129. .controller_data = &mmc_spi_chip_info,
  130. },
  131. #endif
  132. };
  133.  
  134. /* SPI controller data */
  135. static struct bfin5xx_spi_master spi_bfin_master_info = {
  136. .num_chipselect = 8,
  137. .enable_dma = 1, /* master has the ability to do dma transfer */
  138. };
  139.  
  140. static struct platform_device spi_bfin_master_device = {
  141. .name = "bfin-spi-master",
  142. .id = 1, /* Bus number */
  143. .dev = {
  144. .platform_data = &spi_bfin_master_info, /* Passed to driver */
  145. },
  146. };
  147. #endif /* spi master and devices */
  148.  
  149. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  150. #ifdef CONFIG_SERIAL_BFIN_UART0
  151. static struct resource bfin_uart0_resources[] = {
  152. {
  153. .start = BFIN_UART_THR,
  154. .end = BFIN_UART_GCTL+2,
  155. .flags = IORESOURCE_MEM,
  156. },
  157. {
  158. .start = IRQ_UART0_RX,
  159. .end = IRQ_UART0_RX + 1,
  160. .flags = IORESOURCE_IRQ,
  161. },
  162. {
  163. .start = IRQ_UART0_ERROR,
  164. .end = IRQ_UART0_ERROR,
  165. .flags = IORESOURCE_IRQ,
  166. },
  167. {
  168. .start = CH_UART0_TX,
  169. .end = CH_UART0_TX,
  170. .flags = IORESOURCE_DMA,
  171. },
  172. {
  173. .start = CH_UART0_RX,
  174. .end = CH_UART0_RX,
  175. .flags = IORESOURCE_DMA,
  176. },
  177. };
  178.  
  179. unsigned short bfin_uart0_peripherals[] = {
  180. P_UART0_TX, P_UART0_RX, 0
  181. };
  182.  
  183. static struct platform_device bfin_uart0_device = {
  184. .name = "bfin-uart",
  185. .id = 0,
  186. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  187. .resource = bfin_uart0_resources,
  188. .dev = {
  189. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  190. },
  191. };
  192. #endif
  193. #endif
  194.  
  195. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  196. #ifdef CONFIG_BFIN_SIR0
  197. static struct resource bfin_sir0_resources[] = {
  198. {
  199. .start = 0xFFC00400,
  200. .end = 0xFFC004FF,
  201. .flags = IORESOURCE_MEM,
  202. },
  203. {
  204. .start = IRQ_UART0_RX,
  205. .end = IRQ_UART0_RX+1,
  206. .flags = IORESOURCE_IRQ,
  207. },
  208. {
  209. .start = CH_UART0_RX,
  210. .end = CH_UART0_RX+1,
  211. .flags = IORESOURCE_DMA,
  212. },
  213. };
  214.  
  215. static struct platform_device bfin_sir0_device = {
  216. .name = "bfin_sir",
  217. .id = 0,
  218. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  219. .resource = bfin_sir0_resources,
  220. };
  221. #endif
  222. #endif
  223.  
  224. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  225. static struct resource isp1362_hcd_resources[] = {
  226. {
  227. .start = 0x20300000,
  228. .end = 0x20300000 + 1,
  229. .flags = IORESOURCE_MEM,
  230. },{
  231. .start = 0x20300000 + 2,
  232. .end = 0x20300000 + 3,
  233. .flags = IORESOURCE_MEM,
  234. },{
  235. .start = IRQ_PF11,
  236. .end = IRQ_PF11,
  237. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
  238. },
  239. };
  240.  
  241. static struct isp1362_platform_data isp1362_priv = {
  242. .sel15Kres = 1,
  243. .clknotstop = 0,
  244. .oc_enable = 0, /* external OC */
  245. .int_act_high = 0,
  246. .int_edge_triggered = 0,
  247. .remote_wakeup_connected = 0,
  248. .no_power_switching = 1,
  249. .power_switching_mode = 0,
  250. };
  251.  
  252. static struct platform_device isp1362_hcd_device = {
  253. .name = "isp1362-hcd",
  254. .id = 0,
  255. .dev = {
  256. .platform_data = &isp1362_priv,
  257. },
  258. .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
  259. .resource = isp1362_hcd_resources,
  260. };
  261. #endif
  262.  
  263. #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
  264.  
  265.  
  266. #ifdef CONFIG_MTD_PARTITIONS
  267. const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
  268.  
  269. static struct mtd_partition bfin_plat_nand_partitions[] = {
  270. {
  271. .name = "linux kernel(nand)",
  272. .size = 0x800000,
  273. .offset = 0,
  274. }, {
  275. .name = "file system(nand)",
  276. /*.size = MTDPART_SIZ_FULL,*/
  277. .size = (CONFIG_BFIN_NAND_PLAT_SIZE-0x800000),
  278. /*.offset = MTDPART_OFS_APPEND,*/
  279. .offset = 0x800000,
  280. },
  281. };
  282. #endif
  283.  
  284. // #define BFIN_NAND_BASE CONFIG_BFIN_NAND_BASE */
  285. #define BFIN_NAND_BASE CONFIG_BFIN_NAND_PLAT_BASE
  286.  
  287. // #define BFIN_NAND_CLE (1<<CONFIG_BFIN_NAND_CLE) */ /* Ax -> Command Enable */
  288. //#define BFIN_NAND_ALE (1<<CONFIG_BFIN_NAND_ALE) /* Ax -> Address Enable */
  289. #define BFIN_NAND_PLAT_CLE (1<<CONFIG_BFIN_NAND_PLAT_CLE) /* Ax -> Command Enable */
  290. #define BFIN_NAND_PLAT_ALE (1<<CONFIG_BFIN_NAND_PLAT_ALE) /* Ax -> Address Enable */
  291.  
  292. /* #define BFIN_NAND_PLAT_CLE 2
  293. #define BFIN_NAND_PLAT_ALE 1 */
  294. static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  295. {
  296. struct nand_chip *this = mtd->priv;
  297.  
  298. if (cmd == NAND_CMD_NONE)
  299. return;
  300.  
  301. if (ctrl & NAND_CLE)
  302. writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
  303. else
  304. writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
  305. }
  306.  
  307. #define BFIN_NAND_PLAT_READY GPIO_PF3
  308. static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
  309. {
  310. return gpio_get_value(BFIN_NAND_PLAT_READY);
  311. }
  312.  
  313. static struct platform_nand_data bfin_plat_nand_data = {
  314. .chip = {
  315. .nr_chips = 1,
  316. .chip_delay = 30,
  317. #ifdef CONFIG_MTD_PARTITIONS
  318. .part_probe_types = part_probes,
  319. .partitions = bfin_plat_nand_partitions,
  320. .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
  321. #endif
  322. },
  323. .ctrl = {
  324. .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
  325. .dev_ready = bfin_plat_nand_dev_ready,
  326. },
  327. };
  328.  
  329. #define MAX(x, y) (x > y ? x : y)
  330. static struct resource bfin_plat_nand_resources = {
  331. .start = 0x20212000,
  332. .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
  333. .flags = IORESOURCE_MEM,
  334. };
  335.  
  336. static struct platform_device bfin_async_nand_device = {
  337. .name = "gen_nand",
  338. .id = -1,
  339. .num_resources = 1,
  340. .resource = &bfin_plat_nand_resources,
  341. .dev = {
  342. .platform_data = &bfin_plat_nand_data,
  343. },
  344. };
  345.  
  346. static void bfin_plat_nand_init(void)
  347. {
  348. gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
  349. }
  350. #else
  351. static void bfin_plat_nand_init(void) {}
  352. #endif
  353.  
  354. static struct platform_device *ip0x_devices[] __initdata = {
  355. #if defined(CONFIG_BFIN532_IP0X)
  356. #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
  357. &dm9000_device1,
  358. &dm9000_device2,
  359. #endif
  360. #endif
  361.  
  362. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  363. &spi_bfin_master_device,
  364. #endif
  365.  
  366. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  367. #ifdef CONFIG_SERIAL_BFIN_UART0
  368. &bfin_uart0_device,
  369. #endif
  370. #endif
  371.  
  372. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  373. #ifdef CONFIG_BFIN_SIR0
  374. &bfin_sir0_device,
  375. #endif
  376. #endif
  377.  
  378. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  379. &isp1362_hcd_device,
  380. #endif
  381.  
  382. #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
  383. &bfin_async_nand_device,
  384. #endif
  385. };
  386.  
  387. static int __init ip0x_init(void)
  388. {
  389. int i;
  390.  
  391. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  392. platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
  393.  
  394. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  395. for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) {
  396. int j = 1 << bfin_spi_board_info[i].chip_select;
  397. /* set spi cs to 1 */
  398. bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j);
  399. bfin_write_FIO_FLAG_S(j);
  400. }
  401. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  402. #endif
  403.  
  404. return 0;
  405. }
  406.  
  407. arch_initcall(ip0x_init);
  408.  
  409. static struct platform_device *ip0x_early_devices[] __initdata = {
  410. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  411. #ifdef CONFIG_SERIAL_BFIN_UART0
  412. &bfin_uart0_device,
  413. #endif
  414. #endif
  415. };
  416.  
  417. void __init native_machine_early_platform_add_devices(void)
  418. {
  419. printk(KERN_INFO "register early platform devices\n");
  420. early_platform_add_devices(ip0x_early_devices,
  421. ARRAY_SIZE(ip0x_early_devices));
  422. }
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